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  Vigyan Singhal

Vigyan founded Oski Technology in January 2006. He serves on Technical Advisory Boards at Cypress Semiconductor and PwrLite. Previously, he had founded the formal verification EDA company, Jasper Design Automation, where he was the President and CEO from 1999 to 2003. Earlier, he was a Research Scientist at Cadence Design Systems. He has also been an instructor for design verification classes at the University of California Santa Cruz extension. Vigyan received a Ph.D. from the University of California at Berkeley, where he was a Regents fellow. He also has a B.Tech. in Computer Science and Engineering from the Indian Institute of Technology at Kanpur.
 
       
    Recent methodology papers

 
   
A. Datta, V. Singhal. Formal verification of a public-domain DDR2 controller design. VLSI Design January 2008, Hyderabad, India.
V. Singhal, H. D. Foster. Who verifies your third-party design IP?. IEEE CEDA Currents May 2006, pp. 3-4. Also see responses from Tensilica and Real Intent.
H. D. Foster, L. Loh, B. Rabii, V. Singhal. Guidelines for creating a formal verification testplan. DVCon February 2006, San Jose, CA. (Talk)
V. Singhal, J. E. Higgins. Compliance verification for SoC and IP interfaces. DesignCon January 2002, San Jose, CA.
 
       
    Recent talks

 
   
Commercial formal verification. December 2006.
Formal verification for PCI Express RTL designs. PCI-SIG Developers Conference, June 2006.
Coverage: the link between simulation and formal. May 2006.
PSL (Property Specification Language). UC Berkeley CAD Group, April 2005 (with Harry Foster).
 
       
    Some past academic papers

 
   
V. Singhal, A. Aziz, C. Pixley, R. K. Brayton. Theory of safe replacements for sequential circuits. IEEE Trans. Computer-Aided Design, vol. 20, no. 2, February 2001. 
M. Ganai, P. Yalagandula, A. Aziz, A. Kuehlmann, V. Singhal. SIVA: a system for coverage-directed search. J. Electronic Testing: Theory and Applications (JETTA), February 2001.
J. Baumgartner, T. Heyman, V. Singhal, A. Aziz. Model-checking the IBM Gigahertz processor: an abstraction algorithm for high-performance netlists. CAV 1999, Trento, Italy.
J. R. Burch, V. Singhal. Tight integration of combinational verification methods. ICCAD 1998, San Jose, CA.
V. Singhal, C. Pixley, R. L. Rudell, R. K. Brayton. The validity of retiming sequential circuits. DAC 1995, San Francisco, CA.
 
       
       
       
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